The present invention relates in general to a method of fabricating a memory device, and more particularly, to a method of fabricating a memory device with a recessed gate.
In the rapidly evolving integrated circuit industry there is a development tendency toward high performance, miniaturization, and high operating speed. Additionally dynamic random access memory (DRAM) fabrication methods have developed rapidly.
Typically, current dynamic random access memory DRAM cells include a transistor and a capacitor. Since the capacity of current DRAM has reached 256 MB and up to 512 MB, the size of memory cells and transistors has narrowed to meet demands for high integration, higher memory capacity and higher operating speeds. In conventional planar transistor technology, however, more useable surface area on a chip is required, and it is difficult to meet the previously mentioned demands. Accordingly, recessed gate and channel technology has been applied to DRAM fabrication with the goal of reducing the area occupied by the transistor and the capacitor on the semiconductor substrate. The conventional planar transistor technology requires a large amount of surface area on the chip, and cannot accomplish the demand for high integration. Conversely, the disadvantages of the conventional semiconductor memory cell can be improved by applying recessed vertical gate transistor RVERT technology to DRAM fabrication. And the RVERT technology is positioned to become a major semiconductor memory cell fabrication method.
FIG. 1 is a top view of conventional vertical gate transistor. Referring to FIG. 1, a distance between a recessed gate and a deep trench capacitor 104 is required to be controlled precisely due to requirement for controlling out diffusion distance D. The overlay control of forming recessed gate in conventional lithography process, however, is very tight when process generation is 60 nm or further.